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CS2100-CP - Fractional-N Clock Multiplier

Datasheet Summary

Description

The CS2100-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop.

The CS2100-CP is based on a hybrid analog-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL.

Features

  •  Clock Multiplier / Jitter Reduction      Generates a Low Jitter 6 - 75 MHz Clock from a Jittery or Intermittent 50 Hz to 30 MHz Clock Source Highly Accurate PLL Multiplication Factor.
  • Maximum Error Less Than 1 PPM in HighResolution Mode ® I²C / SPI™ Control Port Configurable Auxiliary Output Flexible Sourcing of Reference Clock.
  • External Oscillator or Clock Source.
  • Supports Inexpensive Local Crystal Minimal Board Space Required.
  • No External Analog L.

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Datasheet preview – CS2100-CP

Datasheet Details

Part number CS2100-CP
Manufacturer Cirrus Logic
File Size 447.29 KB
Description Fractional-N Clock Multiplier
Datasheet download datasheet CS2100-CP Datasheet
Additional preview pages of the CS2100-CP datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com CS2100-CP Fractional-N Clock Multiplier General Description The CS2100-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2100-CP is based on a hybrid analog-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for generation of a low-jitter clock relative to an external noisy synchronization clock at frequencies as low as 50 Hz. The CS2100-CP supports both I²C and SPI for full software control. The CS2100-CP is available in a 10-pin MSOP package in Commercial (-10°C to +70°C) grade. Customer development kits are also available for device evaluation. Please see “Ordering Information” on page 32 for complete details.
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